I would like to preface this with the fact that I hate this new change. As a professional FPGA Engineer, who has exclusively used Xilinx parts for most of my career, I figured I’d offer my two cents.
Vivado was never open source to begin with. So I don’t see how this would allow more back doors to be in the program, and I’m also not sure what you mean by a back door in this context. Do you mean making Vivado install back doors into the bitstreams themselves? If so, this would be difficult to do given there are independent tools out there that allow you to verify what is in the compiled netlist (which is an intermediate step in a design) vs the HDL (Hardware Description Language, the type of Language that is used to program FPGAs, main ones are VHDL and Verilog). There’s also some new tools coming out do compare the bitstream against the net list. With these tools, you can all but guarantee there aren’t any back doors or Trojans in the design.
Vivado is also already export controlled IIRC. At the very least, you’ve always had to input your country/address/etc due to controls on it. I’m in the USA, so it’s never been a problem, so I don’t really know what happens for people in, say, China. It might just be for logging/tracking purposes, and then in the future it could get locked down, so you may be right on that count.
I would like to preface this with the fact that I hate this new change. As a professional FPGA Engineer, who has exclusively used Xilinx parts for most of my career, I figured I’d offer my two cents.
Vivado was never open source to begin with. So I don’t see how this would allow more back doors to be in the program, and I’m also not sure what you mean by a back door in this context. Do you mean making Vivado install back doors into the bitstreams themselves? If so, this would be difficult to do given there are independent tools out there that allow you to verify what is in the compiled netlist (which is an intermediate step in a design) vs the HDL (Hardware Description Language, the type of Language that is used to program FPGAs, main ones are VHDL and Verilog). There’s also some new tools coming out do compare the bitstream against the net list. With these tools, you can all but guarantee there aren’t any back doors or Trojans in the design.
Vivado is also already export controlled IIRC. At the very least, you’ve always had to input your country/address/etc due to controls on it. I’m in the USA, so it’s never been a problem, so I don’t really know what happens for people in, say, China. It might just be for logging/tracking purposes, and then in the future it could get locked down, so you may be right on that count.
Those Xilinx USB programmers are such a pain in the ass to use. They tend to work fine like 95% of the time but the other 5% just refuse to work.